//////////////////////////////////////////////////////////////////////////    
// Copyright (c)2016 ALTA Incorporated                                     //    
// All Rights Reserved                                                     //    
// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE of ALTA Inc.                //    
// The copyright notice above does not evidence any actual or intended     //    
// publication of such source code.                                        //    
// No part of this code may be reproduced, stored in a retrieval system,   //    
// or transmitted, in any form or by any means, electronic, mechanical,    //    
// photocopying, recording, or otherwise, without the prior written        //    
// permission of ALTA                                                      //    
/////////////////////////////////////////////////////////////////////////////    
/////////////////////////////////////////////////////////////////////////////    
// Name of module : alta_mcu_top                                           //    
// Func           : top level                                              //    
// Author         : yinliang                                               //    
// Simulator      : Ncverilog/LINUX64                                      //    
// Synthesizer    : DC_2010 /LINUX64                                       //     
// version 1.0    : made in Date: 2016.01.10                               //    
/////////////////////////////////////////////////////////////////////////////    

`timescale 1ns/10ps        
module alta_mcu_top    (//inputs                               
                    	//clock and reset                    
                    	input  wire        CLK                  ,//when power on, it is free running                           
                    	input  wire        JTCK                 ,                          
                    	input  wire        POR_n                ,                         
                    	input  wire        EXT_CPU_RST_n        ,                 
                    	input  wire        JTRST_n              ,                       
                    	//uart                                             
                    	input  wire        UART_RXD             ,                      
                    	input  wire        UART_CTS_n           ,                    
                    	//jtag                                            
                    	input  wire        JTDI                 ,                          
                    	input  wire        JTMS                 ,                          
                    	//ram access                               
                    	input  wire        EXT_RAM_EN           ,                    
                    	input  wire        EXT_RAM_WR           ,                    
                    	input  wire [13:0] EXT_RAM_ADDR         ,	//in word
                    	input  wire [3:0]  EXT_RAM_BYTE_EN      ,         
                    	input  wire [31:0] EXT_RAM_WDATA        ,          
                    	//flash                                    
                    	input  wire [23:0] FLASH_BIAS           ,             
                    		//ext ahb slave                          
                    	input  wire [1:0]  HRESP_EXT,                     
                    	input  wire        HREADY_OUT_EXT       ,                
                    	input  wire [31:0] HRDATA_EXT           ,             
                      output wire [1:0]  HTRANS_EXT           ,             
                    	output wire [31:0] HADDR_EXT            ,             
                    	output wire        HWRITE_EXT           ,                   
                    	output wire        HSEL_EXT             ,                     
                    	output wire [31:0] HWDATA_EXT           ,            
                    	output wire [2:0]  HSIZE_EXT            ,               
                    	output wire        HREADY_IN_EXT        ,	               
                    //outputs                                    
                    	//flash                                    
                    	output wire        FLASH_SCK            ,                    
                    	output wire        FLASH_CS_n           ,                   
                    	//uart                                     
                    	output wire        UART_TXD             ,                     
                    	output wire        UART_RTS_n           ,                   
                    	//jtag                                     
                    	output wire        JTDO                 ,                         
                    	//ram access                               
                    	output wire [31:0] EXT_RAM_RDATA        ,         
                    	//flash                                  
                    	output wire        FLASH_IO0_SI         ,                 
                    	output wire        FLASH_IO1_SO         ,                 
                    	output wire        FLASH_IO2_WPn        ,                
                    	output wire        FLASH_IO3_HOLDn      ,              
                    	input  wire        FLASH_IO0_SI_i       ,               
                    	input  wire        FLASH_IO1_SO_i       ,               
                    	input  wire        FLASH_IO2_WPn_i      ,              
                    	input  wire        FLASH_IO3_HOLDn_i    ,            
                    	output wire        FLASH_SI_OE          ,              
                    	output wire        FLASH_SO_OE          ,              
                    	output wire        WPn_IO2_OE           ,                
                    	output wire        HOLDn_IO3_OE         ,		    			   
                    	//gpio                                   
                    	input  wire [7:0]  GPIO0_I              ,                
                    	input  wire [7:0]  GPIO1_I              ,                
                    	input  wire [7:0]  GPIO2_I              ,                
                    	output wire [7:0]  GPIO0_O              ,                
                    	output wire [7:0]  GPIO1_O              ,                
                    	output wire [7:0]  GPIO2_O              ,                
                    	output wire [7:0]  nGPEN0               ,                 
                    	output wire [7:0]  nGPEN1               ,                 
                    	output wire [7:0]  nGPEN2			          ,
                    	output wire        O_INI_IP,              //high indicate ini mcu remap register is in progress        
                    	output wire [31:0] tout    
                    );    
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
wire       TCK_INI                                                    ;
wire       TMS_INI                                                    ;
wire       TDI_INI                                                    ;
wire       TDO_INI                                                    ;                       
                                                                      
                                                                      
wire       TCK_MUX                                                    ;      
wire       TMS_MUX                                                    ;
wire       TDI_MUX                                                    ; 
wire       TDO                                                        ;


assign     TCK_MUX = O_INI_IP ? TCK_INI : JTCK                        ;
assign     TMS_MUX = O_INI_IP ? TMS_INI : JTMS                        ;
assign     TDI_MUX = O_INI_IP ? TDI_INI : JTDI                        ;
                                                                      
assign     TDO_INI = O_INI_IP ? TDO :     1'b0                        ;
                                                                      
assign     JTDO    = O_INI_IP ? 1'b0 :    TDO                         ;
                                                                      
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////                                                                      
wire FLASH_SCK_MCU                                                    ;
                                                                      
wire FLASH_CSN_MCU                                                    ;
                                                                                                                                            
wire FLASH_SO_OE_MCU                                                  ;
                                                                      
wire FLASH_IO0_SI_MCU                                                 ;  
                                                                      
wire FLASH_IO1_SO_i_MCU                                               ;

 
wire FLASH_CSN                                                        ; 
wire FLASH_SCLK                                                       ; 
wire FLASH_SDI                                                        ;  
wire FLASH_SDO                                                        ; 

 
assign  FLASH_SCK          = O_INI_IP ? FLASH_SCLK : FLASH_SCK_MCU    ;    
assign  FLASH_CS_n         = O_INI_IP ? FLASH_CSN  : FLASH_CSN_MCU    ;
                           
assign  FLASH_IO0_SI       = O_INI_IP ? FLASH_SDI : FLASH_IO0_SI_MCU  ;         
                           
assign  FLASH_SO_OE        = O_INI_IP ? 1'b0   :     FLASH_SO_OE_MCU  ;
                           
assign  FLASH_SDO          = O_INI_IP ? FLASH_IO1_SO_i : 1'b0         ;

assign  FLASH_IO1_SO_i_MCU = O_INI_IP ? 1'b0 : FLASH_IO1_SO_i         ;  
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 

wire        RAM_WR                                                    ;
wire [13:0] RAM_ADDR                                                  ;
wire [3:0]  RAM_BYTE_EN                                               ;
wire [31:0] RAM_WDATA                                                 ;


wire        EXT_RAM_EN_MCU                                            ; 
wire        EXT_RAM_WR_MCU                                            ; 
wire [13:0] EXT_RAM_ADDR_MCU                                          ; 
wire [3:0]  EXT_RAM_BYTE_EN_MCU                                       ; 
wire [31:0] EXT_RAM_WDATA_MCU                                         ; 


assign EXT_RAM_EN_MCU      = O_INI_IP ? 1'b1        : EXT_RAM_EN      ; 
assign EXT_RAM_WR_MCU      = O_INI_IP ? RAM_WR      : EXT_RAM_WR      ;
assign EXT_RAM_ADDR_MCU    = O_INI_IP ? RAM_ADDR    : EXT_RAM_ADDR    ;
assign EXT_RAM_BYTE_EN_MCU = O_INI_IP ? 4'b1111     : EXT_RAM_BYTE_EN ;
assign EXT_RAM_WDATA_MCU   = O_INI_IP ? RAM_WDATA   : EXT_RAM_WDATA   ;




////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 

alta_mcu   u_alta_mcu   (                               
                         .CLK               (CLK                ),
                         .JTCK              (TCK_MUX            ),
                         .POR_n             (POR_n              ),
                         .EXT_CPU_RST_n     (EXT_CPU_RST_n      ),
                         .JTRST_n           (JTRST_n            ),
                         .UART_RXD          (UART_RXD           ),
                         .UART_CTS_n        (UART_CTS_n         ),
                         .JTDI              (TDI_MUX            ),
                         .JTMS              (TMS_MUX            ),
                         .EXT_RAM_EN        (EXT_RAM_EN_MCU     ),
                         .EXT_RAM_WR        (EXT_RAM_WR_MCU     ),
                         .EXT_RAM_ADDR      (EXT_RAM_ADDR_MCU   ),
                         .EXT_RAM_BYTE_EN   (EXT_RAM_BYTE_EN_MCU),
                         .EXT_RAM_WDATA     (EXT_RAM_WDATA_MCU  ),
                         .FLASH_BIAS        (FLASH_BIAS         ),
                         .HRESP_EXT         (HRESP_EXT          ),
                         .HREADY_OUT_EXT    (HREADY_OUT_EXT     ),
                         .HRDATA_EXT        (HRDATA_EXT         ),
                         .HTRANS_EXT        (HTRANS_EXT         ),
                         .HADDR_EXT         (HADDR_EXT          ),
                         .HWRITE_EXT        (HWRITE_EXT         ),
                         .HSEL_EXT          (HSEL_EXT           ),
                         .HWDATA_EXT        (HWDATA_EXT         ),
                         .HSIZE_EXT         (HSIZE_EXT          ),
                         .HREADY_IN_EXT     (HREADY_IN_EXT      ),
                         .FLASH_SCK         (FLASH_SCK_MCU      ),
                         .FLASH_CS_n        (FLASH_CSN_MCU      ),
                         .UART_TXD          (UART_TXD           ),
                         .UART_RTS_n        (UART_RTS_n         ),
                         .JTDO              (TDO                ),
                         .EXT_RAM_RDATA     (EXT_RAM_RDATA      ),
                         .FLASH_IO0_SI      (FLASH_IO0_SI_MCU   ),
                         .FLASH_IO1_SO      (FLASH_IO1_SO       ),
                         .FLASH_IO2_WPn     (FLASH_IO2_WPn      ),
                         .FLASH_IO3_HOLDn   (FLASH_IO3_HOLDn    ),
                         .FLASH_IO0_SI_i    (FLASH_IO0_SI_i     ),
                         .FLASH_IO1_SO_i    (FLASH_IO1_SO_i_MCU ),
                         .FLASH_IO2_WPn_i   (FLASH_IO2_WPn_i    ),
                         .FLASH_IO3_HOLDn_i (FLASH_IO3_HOLDn_i  ),
                         .FLASH_SI_OE       (FLASH_SI_OE        ),
                         .FLASH_SO_OE       (FLASH_SO_OE_MCU    ),
                         .WPn_IO2_OE        (WPn_IO2_OE         ),
                         .HOLDn_IO3_OE      (HOLDn_IO3_OE       ),
                         .GPIO0_I           (GPIO0_I            ),
                         .GPIO1_I           (GPIO1_I            ),
                         .GPIO2_I           (GPIO2_I            ),
                         .GPIO0_O           (GPIO0_O            ),
                         .GPIO1_O           (GPIO1_O            ),
                         .GPIO2_O           (GPIO2_O            ),
                         .nGPEN0            (nGPEN0             ),
                         .nGPEN1            (nGPEN1             ),
                         .nGPEN2            (nGPEN2             )
                    );                                          
                                                                
                                                                
mcu_ini_cfg  u_mcu_ini_cfg (.i_clk          (CLK                ), 
                            .i_reset_n      (POR_n              ),
                            .i_flash_bias   (FLASH_BIAS         ),
                            .o_tck          (TCK_INI            ),
                            .o_tms          (TMS_INI            ),
                            .o_tdi          (TDI_INI            ),
                            .i_tdo          (TDO_INI            ),
                            .o_flash_csn    (FLASH_CSN          ),
                            .o_flash_sclk   (FLASH_SCLK         ),
                            .o_flash_sdi    (FLASH_SDI          ),
                            .i_flash_sdo    (FLASH_SDO          ),  
                            //.o_flash_si_oe  (FLASH_SIoe         ), 
                            .o_ram_wr       (RAM_WR             ),
                            .o_ram_addr     (RAM_ADDR           ),
                            .o_ram_wdata    (RAM_WDATA          ),                                                                                                        
                            .o_ini_ip       (O_INI_IP           )
                           );


assign tout = {FLASH_SDO, FLASH_SDI, FLASH_SCLK, FLASH_CSN, TDO, TDI_MUX, TMS_MUX, TCK_MUX, O_INI_IP, CLK, POR_n};

endmodule                                                                                             
